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rail-to-rail, very fast, 2.5 v to 5.5 v, single-supply ttl/cmos comparators adcmp600/adcmp601/adcmp602 features functional block diagram noninverting input inverting input le/hys (except adcmp600) q output s dn (adcmp602 only) adcmp600/ adcmp601/ adcmp602 05914-001 fully specified rail to rail at v cc = 2.5 v to 5.5 v input common-mode voltage from ?0.2 v to v cc + 0.2 v low glitch cmos-/ttl-compatible output stage 3.5 ns propagation delay 10 mw at 3.3 v shutdown pin single-pin control for programmable hysteresis and latch power supply rejection > 50 db improved replacement for max999 figure 1. ?40c to +125c operation applications high speed instrumentation clock and data signal restoration logic level shifting or translation pulse spectroscopy high speed line receivers threshold detection peak and zero-crossing detectors high speed trigger circuitry pulse-width modulators current/voltage-controlled oscillators automatic test equipment (ate) general description the adcmp600, adcmp601, and adcmp602 are very fast comparators fabricated on xfcb2, an analog devices, inc. proprietary process. these comparators are exceptionally versatile and easy to use. features include an input range from v ee ? 0.5 v to v cc + 0.2 v, low noise, ttl-/cmos-compatible output drivers, and latch inputs with adjustable hysteresis and/or shutdown inputs. the device offers 5 ns propagation delay with 10 mv overdrive on 3 ma typical supply current. a flexible power supply scheme allows the devices to operate with a single +2.5 v positive supply and a ?0.5 v to +2.8 v input signal range up to a +5.5 v positive supply with a ?0.5 v to +5.8 v input signal range. split input/output supplies with no sequencing restrictions on the adcmp602 support a wide input signal range while still allowing independent output swing control and power savings. the ttl-/cmos-compatible output stage is designed to drive up to 5 pf with full timing specs and to degrade in a graceful and linear fashion as additional capacitance is added. the comparator input stage offers robust protection against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. latch and programmable hysteresis features are also provided with a unique single-pin control option. the adcmp600 is available in 5-lead sc70 and sot-23 packages, the adcmp601 is available in a 6-lead sc70 package, and the adcmp602 is available in an 8-lead msop package. rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved.
adcmp600/adcmp601/adcmp602 rev. 0 | page 2 of 16 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 electrical characteristics............................................................. 3 timing information ......................................................................... 5 absolute maximum ratings............................................................ 6 thermal resistance ...................................................................... 6 pin configuration and function descriptions............................. 7 typical performance characteristics ............................................. 8 application information................................................................ 10 power/ground layout and bypassing..................................... 10 ttl-/cmos-compatible output stage ................................. 10 using/disabling the latch feature........................................... 10 optimizing performance........................................................... 11 comparator propagation delay dispersion ........................... 11 comparator hysteresis .............................................................. 11 crossover bias point .................................................................. 12 minimum input slew rate requirement ................................ 12 typical application circuits ......................................................... 13 outline dimensions ....................................................................... 14 ordering guide .......................................................................... 14 revision history 10/06revision 0: initial version
adcmp600/adcmp601/adcmp602 rev. 0 | page 3 of 16 specifications electrical characteristics v cci = v cco = 2.5 v, t a = 25c, unless otherwise noted. table 1. parameter symbol conditions min typ max unit dc input characteristics voltage range v p , v n v cc = 2.5 v to 5.5 v ?0.5 v cc + 0.2 v common-mode range v cc = 2.5 v to 5.5 v ?0.2 v cc + 0.2 v differential voltage v cc = 2.5 v to 5.5 v v cc + 0.8 v offset voltage v os ?5.0 2 +5.0 mv bias current i p , i n ?5.0 2 +5.0 a offset current ?2.0 +2.0 a capacitance c p , c n 1 pf resistance, differential mode ?0.1 v to v cc 200 700 k resistance, common mode ?0.5 v to v cc + 0.5 v 100 350 k active gain a v 85 db v cci = 2.5 v, v cco = 2.5 v, v cm = ?0.2 v to +2.7 v 50 db common-mode rejection ratio cmrr v cci = 2.5 v, v cco = 5.5 v 50 db hysteresis (adcmp600) 2 mv hysteresis (adcmp601/adcmp602) r hys = 0.1 mv latch enable pin characteristics (adcmp601/adcmp602 only) v ih hysteresis is shut off 2.0 v cc v v il latch mode guaranteed ?0.2 +0.4 +0.8 v i ih v ih = v cc ?6 +6 a i ol v il = 0.4 v ?0.1 +0.1 ma hysteresis mode and timing (adcmp601/adcmp602 only) hysteresis mode bias voltage current ?1 a 1.145 1.25 1.35 v resistor value hysteresis = 120 mv 65 80 120 k hysteresis current hysteresis = 120 mv ?18 ?12 ?7 a latch setup time t s v od = 50 mv ?2 ns latch hold time t h v od = 50 mv 2.6 ns latch-to-output delay t ploh , t plol v od = 50 mv 27 ns latch minimum pulse width t pl v od = 50 mv 21 ns shutdown pin characteristics (adcmp602 only) v ih comparator is operating 2.0 v cco v v il shutdown guaranteed ?0.2 +0.4 +0.6 v i ih v ih = v cc ?6 6 a i ol v il = 0 v ?100 a sleep time t sd i cco < 500 a 20 ns wake-up time t h v od = 100 mv, output valid 50 ns dc output characteristics v cco = 2.5 v to 5.5 v output voltage high level v oh i oh = 8 ma, v cco = 2.5 v v cc ? 0.4 v output voltage low level v ol i ol = 8 ma, v cco = 2.5 v 0.4 v output voltage high level at ?40c v oh i oh = 6 ma, v cco = 2.5 v v cc ? 0.4 v output voltage low level at? 40c v ol i ol = 6 ma, v cco = 2.5 v 0.4 v
adcmp600/adcmp601/adcmp602 rev. 0 | page 4 of 16 parameter symbol conditions min typ max unit ac performance 1 rise time /fall time t r t f 10% to 90%, v cco = 2.5 v 2.2 ns 10% to 90%, v cco = 5.5 v 4 ns propagation delay t pd v od = 50 mv, v cco = 2.5 v 3.5 ns v od = 50 mv, v cco = 5.5 v 4.3 ns v od = 10 mv, v cco = 2.5 v 5 ns propagation delay skewrising to falling transition v cco = 2.5 v to 5.5 v v od = 50 mv 500 ps overdrive dispersion 10 mv < v od < 125 mv 1.2 ns common-mode dispersion ?0.2 v < v cm < v cci + 2 v v od = 50 mv 200 ps minimum pulse width pw min v cci = v cco = 2.5 v pw out = 90% of pw in 3 ns v cci = v cco = 5.5 v pw out = 90% of pw in 4.5 ns power supply input supply voltage range v cci 2.5 5.5 v output supply voltage range v cco 2.5 5.5 v positive supply differential v cci ? v cco operating ?3.0 +3.0 v (adcmp602 only) v cci ? v cco nonoperating ?5.5 +5.5 v positive supply current (adcmp600/adcmp601) i vcc v cc = 2.5 v v cc = 5.5 v 3 3.5 3.5 4.0 ma input section supply current i vcci v cci = 2.5 v 0.9 1.4 ma (adcmp602 only) v cci = 5.5 v 1.2 2.0 ma output section supply current i vcco v cco = 2.5 v 1.45 3.0 ma (adcmp602 only) v cco = 5.5 v 2.1 3.5 ma power dissipation p d v cc = 2.5 v 7 9 mw p d v cc = 5.5 v 20 23 mw power supply rejection ratio psrr v cci = 2.5 v to 5 v ?50 db shutdown mode i cci v cc = 2.5 v 240 400 a (adcmp602 only) shutdown mode i cco v cc =2.5 v 30 a (adcmp602 only) 1 v in = 100 mv square input at 50 mhz, v cm = 0 v, cl = 5 pf, v cci = v cco =2.5 v, unless otherwise noted.
adcmp600/adcmp601/adcmp602 rev. 0 | page 5 of 16 timing information figure 2 illustrates the adcmp600/adcmp601/adcmp602 latch timing relationships. table 2 provides definitions of the terms shown in figure 2. 1.1v 50% v n v os differential input voltage latch enable q output t h t pdl t ploh t f v in v od t s t pl 05914-025 figure 2. system timing diagram table 2. timing descriptions smbol timing description t pdh input to output high delay propagation delay measured from the time th e input signal crosses the reference ( the input offset voltage) to the 50% point of an output low-to-high transition. t pdl input to output low delay propagation delay measured from the time th e input signal crosses the reference ( the input offset voltage) to the 50% point of an output high-to-low transition. t ploh latch enable to output high delay propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output low-to-high transition. t plol latch enable to output low delay propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output high-to-low transition. t h minimum hold time minimum time after the negative transition of the latch enable signal that the input signal must remain unchanged to be ac quired and held at the outputs. t pl minimum latch enable pulse width minimum time that the latch enable signal must be high to acquire an input signal change. t s minimum setup time minimum time before the negative transition of the latch enable signal occurs that an input signal change must be present to be acquired and held at the outputs. t r output rise time amount of time required to transition from a low to a high output as measured at the 20% and 80% points. t f output fall time amount of time required to transition from a high to a low output as measured at the 20% and 80% points. v od voltage overdrive difference between the input voltages v a and v b .
adcmp600/adcmp601/adcmp602 rev. 0 | page 6 of 16 absolute maximum ratings table 3. parameter rating stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. supply voltages input supply voltage (v cci to gnd) ?0.5 v to +6.0 v ?0.5 v to +6.0 v output supply voltage (v cco to gnd) ?6.0 v to +6.0 v positive supply differential (v cci ? v cco ) thermal resistance input voltages ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. input voltage ?0.5 v to v cci + 0.5 v differential input voltage (v cci + 0.5 v) table 4. thermal resistance maximum input/output current 50 ma shutdown control pin package type ja 1 unit applied voltage (hys to gnd) ?0.5 v to v cco + 0.5 v adcmp600 sc70 5-lead 426 c/w maximum input/output current 50 ma latch/hysteresis control pin applied voltage (hys to gnd) ?0.5 v to v cco + 0.5 v maximum input/output current 50 ma output current 50 ma temperature operating temperature, ambient ?40c to +125c operating temperature, junction 150c storage temperature range ?65c to +150c adcmp600 sot-23 5-lead 302 c/w adcmp601 sc70 6-lead 426 c/w adcmp602 msop 5-lead 130 c/w 1 measurement in still air. esd caution
adcmp600/adcmp601/adcmp602 rev. 0 | page 7 of 16 pin configuration and fu nction descriptions q 1 v p 3 v ee 2 v cci /v cco 5 v n 4 adcmp600 top view (not to scale) 05914-002 q 1 v ee 2 v p 3 v cci /v cco 6 le/hys 5 v n 4 adcmp601 top view (not to scale) 05914-003 v cci 1 v p 2 v n 3 s dn 4 v cco 8 q 7 v ee 6 le/hys 5 adcmp602 top view (not to scale) 05914-004 figure 3. adcmp600 pin configuration figure 4. adcmp601 pin configuration figure 5. adcmp602 pin configuration table 5. adcmp600 (sot-23-5 and sc 70-5) pin function descriptions pin o. mnemonic description 1 q noninverting output. q is at logic high if th e analog voltage at the noninverting input, v p , is greater than the analog voltage at the inverting input, v n . 2 v ee negative supply voltage. 3 v p noninverting analog input. 4 v n inverting analog input. 5 v cci /v cco input section supply/output se ction supply. shared pin. table 6. adcmp601 (sc70-6) pin function descriptions pin o. mnemonic description 1 q noninverting output. q is at logic high if th e analog voltage at the noninverting input, v p , is greater than the analog voltage at the inverting input, v n , if the comparator is in compare mode. 2 v ee negative supply voltage. 3 v p noninverting analog input. 4 v n inverting analog input. 5 le/hys latch/hysteresis control. bias with resistor or current for hysteresis adjustment; drive low to latch. 6 v cci /v cco input section supply/output se ction supply. shared pin. table 7. adcmp602 (msop-8) pin function descriptions pin o. mnemonic description 1 v cci input section supply. 2 v p noninverting analog input. 3 v n inverting analog input. 4 s dn shutdown. drive this pin low to shut down the device. 5 le/hys latch/hysteresis control. bias with resistor or current for hysteresis adjustment; drive low to latch. 6 v ee negative supply voltage. 7 q noninverting output. q is at logic high if th e analog voltage at the noninverting input, v p , is greater than the analog voltage at the inverting input, v n , if the comparator is in compare mode. 8 v cco output section supply.
adcmp600/adcmp601/adcmp602 rev. 0 | page 8 of 16 typical performance characteristics v cci = v cco = 2.5 v, t a = 25c, unless otherwise noted. 20 ?5 5 0 ?10 10 ?15 15 ?20 ?1.0 ?0.2 0.2 0.6 ?0.6 1.01.41.82.22.63.03.4 09514-011 load current (ma) v out (v) i oh vs v oh i ol vs v ol ?800 ?101234 567 ?600 ?400 ?200 0 200 400 600 800 05914-007 current (a) le/hys (v) v cc = 5.5v v cc = 2.5v figure 6. le/hys pin i/v characteristics figure 9. v oh /v ol vs. current load 150 ?150 ?100 ?50 0 50 100 ?1 1 0235 47 6 05914-027 current (a) shutdown pin voltage (v) v cc = 2.5v v cc = 5.5v 0 50 150 250 450 350 550 650 50 100 150 200 250 05914-008 hysteresis (mv) hysteresis resistor (k ? ) v cc = 5.5v v cc = 2.5v figure 7. s dn pin i/v characteristics figure 10. hysteresis vs. r hys control resistor 450 0 50 100 150 200 250 300 350 400 0 ?5 ?10 ?15 ?20 05914-026 hysteresis (mv) pin current (a) lot 1 lot 2 05914-005 i b (a) common-mode voltage (v) ?20 ?15 15 ?10 10 ?5 5 0 20 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 i b @ +125c i b @ +25c v cc = 2.5v i b @ ?40c figure 11. hysteresis vs. pin current figure 8. input bias current vs. input common mode
adcmp600/adcmp601/adcmp602 rev. 0 | page 9 of 16 05914-012 1.00v/div m4.00ns 4.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 05914-009 propagation delay (ns) overdrive (mv) figure 12. propagation delay vs. input overdrive at v cc = 2.5 v figure 15. 50 mhz output waveform v cc = 5.5 v 4.0 3.8 3.4 3.6 3.2 3.0 ?0.6 0 0.6 1.2 1.8 2.4 3.0 05914-028 propagation delay (ns) common-mode voltage (v) v cm at v cc = 2.5v rise fall 05914-013 500mv/div m4.00ns figure16 . 50 mhz output waveforms @ 2.5 v figure 13. propagation delay vs. input common-mode voltage at v cc = 2.5 v 5.0 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 2.5 3.0 3.5 4.0 6.0 5.5 5.0 4.5 05914-029 propagation delay (ns) v cco (v) rise fall figure 14. propagation delay vs. v cco
adcmp600/adcmp601/adcmp602 rev. 0 | page 10 of 16 application information power/ground layout and bypassing this delay is measured to the 50% point for the supply in use; therefore, the fastest times are observed with the v cc supply at 2.5 v, and larger values are observed when driving loads that switch at other levels. the adcmp600/adcmp601/adcmp602 comparators are very high speed devices. despite the low noise output stage, it is essential to use proper high speed design techniques to achieve the specified performance. because comparators are uncompensated amplifiers, feedback in any phase relationship is likely to cause oscillations or undesired hysteresis. of critical importance is the use of low impedance supply planes, particularly the output supply plane (v cco ) and the ground plane (gnd). individual supply planes are recommended as part of a multilayer board. providing the lowest inductance return path for switching currents ensures the best possible performance in the target application. when duty cycle accuracy is critical, the logic being driven should switch at 50% of v cc and load capacitance should be minimized. when in doubt, it is best to power v cco or the entire device from the logic supply and rely on the input psrr and cmrr to reject noise. overdrive and input slew rate dispersions are not significantly affected by output loading and v cc variations. the ttl-/cmos-compatible output stage is shown in the simplified schematic diagram (figure 17). because of its inherent symmetry and generally good behavior, this output stage is readily adaptable for driving various filters and other unusual loads. it is also important to adequately bypass the input and output supplies. multiple high quality 0.01 f bypass capacitors should be placed as close as possible to each of the v cci and v cco supply pins and should be connected to the gnd plane with redundant vias. at least one of these should be placed to provide a physically short return path for output currents flowing back from ground to the v cc pin. high frequency bypass capacitors should be carefully selected for minimum inductance and esr. parasitic layout inductance should also be strictly controlled to maximize the effectiveness of the bypass at high frequencies. output q2 q1 + in ? in output stage v logic gain stage a2 a1 a v 0 5914-014 if the package allows and the input and output supplies have been connected separately such that v cci v cco , care should be taken to bypass each of these supplies separately to the gnd plane. a bypass capacitor should never be connected between them. it is recommended that the gnd plane separate the v cci and v cco planes when the circuit board layout is designed to minimize coupling between the two supplies and to take advantage of the additional bypass capacitance from each respective supply to the ground plane. this enhances the performance when split input/output supplies are used. if the input and output supplies are connected together for single-supply operation such that v cci = v cco , coupling between the two supplies is unavoidable; however, careful board placement can help keep output return currents away from the inputs. figure 17. simplified schematic diagram of ttl-/cmos-compatible output stage using/disabling the latch feature the latch input is designed for maximum versatility. it can safely be left floating for fixed hysteresis or be tied to v cc to remove the hysteresis, or it can be driven low by any standard ttl/cmos device as a high speed latch. ttl-/cmos-compatible output stage in addition, the pin can be operated as a hysteresis control pin with a bias voltage of 1.25 v nominal and an input resistance of approximately 7000 . this allows the comparator hysteresis to be easily and accurately controlled by either a resistor or an inexpensive cmos dac. specified propagation delay performance can be achieved only by keeping the capacitive load at or below the specified minimums. the outputs of the devices are designed to directly drive one schottky ttl or three low power schottky ttl loads or the equivalent. for large fan outputs, buses, or transmission lines, use an appropriate buffer to maintain the excellent speed and stability of the comparator. hysteresis control and latch mode can be used together if an open drain, an open collector, or a three-state driver is connected parallel to the hysteresis control resistor or current source. with the rated 5 pf load capacitance applied, more than half of the total device propagation delay is output stage slew time, even at 2.5 v v cc . because of this, the total prop delay decreases as v cco decreases, and instability in the power supply may appear as excess delay dispersion. due to the programmable hysteresis feature, the logic threshold of the latch pin is approximately 1.1 v regardless of v cc .
adcmp600/adcmp601/adcmp602 rev. 0 | page 11 of 16 q/q output input voltage 10v/ns 1v/ns dispersion v n v os 05914-016 optimizing performance as with any high speed comparator, proper design and layout techniques are essential for obtaining the specified performance. stray capacitance, inductance, inductive power and ground impedances, or other layout issues can severely limit performance and often cause oscillation. large discontinuities along input and output transmission lines can also limit the specified pulse- width dispersion performance. the source impedance should be minimized as much as is practicable. high source impedance, in combination with the parasitic input capacitance of the comparator, causes an undesirable degradation in bandwidth at the input, thus degrading the overall response. thermal noise from large resistances can easily cause extra jitter with slowly slewing input signals; higher impedances encourage undesired coupling. figure 19. propagation delayslew rate dispersion comparator hysteresis the addition of hysteresis to a comparator is often desirable in a noisy environment, or when the differential input amplitudes are relatively small or slow moving. figure 20 shows the transfer function for a comparator with hysteresis. as the input voltage approaches the threshold (0.0 v, in this example) from below the threshold region in a positive direction, the comparator switches from low to high when the input crosses +v h /2, and the new switching threshold becomes ?v h /2. the comparator remains in the high state until the new threshold, ?v h /2, is crossed from below the threshold region in a negative direction. in this manner, noise or feedback output signals centered on 0.0 v input cannot cause the comparator to switch states unless it exceeds the region bounded by v h /2. comparator propagation delay dispersion the adcmp600/adcmp601/adcmp602 comparators are designed to reduce propagation delay dispersion over a wide input overdrive range. propagation delay dispersion is the variation in propagation delay that results from a change in the degree of overdrive or slew rate (that is, how far or how fast the input signal exceeds the switching threshold). propagation delay dispersion is a specification that becomes important in high speed, time-critical applications, such as data communication, automatic test and measurement, and instru- mentation. it is also important in event-driven applications, such as pulse spectroscopy, nuclear instrumentation, and medical imaging. dispersion is defined as the variation in propagation delay as the input overdrive conditions are changed (figure 18 and figure 19). output input 0 v ol v oh +v h 2 ?v h 2 05914-017 the device dispersion is typically < 2 ns as the overdrive varies from 10 mv to 125 mv. this specification applies to both positive and negative signals because the device has very closely matched delays both positive-going and negative-going inputs. q/q output input voltage 500mv overdrive 10mv overdrive dispersion v n v os 05914-015 figure 20. comparator hysteresis transfer function the customary technique for introducing hysteresis into a comparator uses positive feedback from the output back to the input. one limitation of this approach is that the amount of hysteresis varies with the output logic levels, resulting in hysteresis that is not symmetric about the threshold. the external feedback network can also introduce significant parasitics that reduce high speed performance and induce oscillation in some cases. figure 18. propagation delayoverdrive dispersion these adcmp600 features a fixed hysteresis of approximately 2 mv. the adcmp601 and adcmp602 comparators offer a programmable hysteresis feature that can significantly improve accuracy and stability. connecting an external pull-down resistor or a current source from the le/hys pin to gnd, varies the amount of hysteresis in a predictable, stable manner.
adcmp600/adcmp601/adcmp602 rev. 0 | page 12 of 16 0 50 150 250 450 350 550 650 50 100 150 200 250 05914-030 hysteresis (mv) hysteresis resistor (k ? ) v cc = 5.5v v cc = 2.5v leaving the le/hys pin disconnected results in a fixed hysteresis of 2 mv; driving this pin high removes hysteresis. the maximum hysteresis that can be applied using this pin is approximately 160 mv. figure 21 illustrates the amount of hysteresis applied as a function of the external resistor value, and figure 11 illustrates hysteresis as a function of the current. the hysteresis control pin appears as a 1.25 v bias voltage seen through a series resistance of 7 k 20% throughout the hysteresis control range. the advantages of applying hysteresis in this manner are improved accuracy, improved stability, reduced component count, and maximum versatility. an external bypass capacitor is not recommended on the hys pin because it impairs the latch function and often degrades the ji tter performance of the device. as described in the using/disabling the latch feature section, hysteresis control need not compromise the latch function. figure 21. hysteresis vs. r hys control resistor minimum input slew rate requirement crossover bias point with the rated load capacitance and normal good pc board design practice, as discussed in the optimizing performance section, these comparators should be stable at any input slew rate with no hysteresis. broadband noise from the input stage is observed in place of the violent chattering seen with most other high speed comparators. with additional capacitive loading or poor bypassing, oscillation is observed. this oscillation is due to the high gain bandwidth of the comparator in combination with feedback parasitics in the package and pc board. in many applications, chattering is not harmful. in both op amps and comparators, rail-to-rail inputs of this type have a dual front-end design. certain devices are active near the v cc rail and others are active near the v ee rail. at some predeter- mined point in the common-mode range, a crossover occurs. at this point, normally v cc /2, the direction of the bias current reverses and the measured offset voltages and currents change. the adcmp600/adcmp601/adcmp602 comparators slightly elaborate on this scheme. crossover points can be found at approximately 0.8 v and 1.6 v.
adcmp600/adcmp601/adcmp602 rev. 0 | page 13 of 16 typical application circuits output adcmp600 0.1f 5 v 0.1f 2k ? 2k ? 05914-019 cmos pwm output adcmp600 2.5 v input 1.25v ref input 1.25v 50m v le/hys adcmp601 82pf 10k ? 10k ? 40k ? 10k ? 05914-022 figure 22. self-biased, 50% slicer cmos adcmp600 cmos v dd 2.5v to 5v 100 ? 05914-020 figure 23. lvds-to-cmos receiver figure 25. oscillator and pulse-width modulator adcmp601 2.5v to 5 v 10k ? le/hys digital input hysteresis current 74 ahc 1g07 0 5914-023 output 1.5mhz to 30mhz le/hys adcmp601 2.5 v 82pf 10k ? 100k ? 100k ? 20k ? 20k ? control voltage 0v to 2.5v 05914-021 figure 24. voltage-controlled oscillator figure 26. hysteresis adjustment with latch
adcmp600/adcmp601/adcmp602 rev. 0 | page 14 of 16 outline dimensions compliant to jedec standards mo-203-aa 0.30 0.15 0 . 1 0 m a x 1.00 0.90 0.70 0.46 0.36 0.26 seating plane 0.22 0.08 1.10 0.80 4 5 123 pin 1 0.65 bsc 2.20 2.00 1.80 2.40 2.10 1.80 1.35 1.25 1.15 0.10 coplanarity 0.40 0.10 compliant to jedec standards mo-203-ab 0.22 0.08 0.30 0.15 1.00 0.90 0.70 seating plane 4 5 6 3 2 1 pin 1 0.65 bsc 1.30 bsc 0.10 max 0.10 coplanarity 0.40 0.10 1.10 0.80 2.20 2.00 1.80 2.40 2.10 1.80 1.35 1.25 1.15 0.46 0.36 0.26 figure 27. 5-lead thin shrink small outline transistor package (sc70) (ks-5) dimensions shown in millimeters figure 29. 6-lead thin shrink small outline transistor package (sc70) (ks-6) dimensions shown in millimeters pin 1 1.60 bsc 2.80 bsc 1.90 bsc 0.95 bsc 5 123 4 0.22 0.08 10 5 0 0.50 0.30 0.15 max seating plane 1.45 max 1.30 1.15 0.90 2.90 bsc 0.60 0.45 0.30 compliant to jedec standards mo-178-aa compliant to jedec standards mo-187-aa 0.80 0.60 0.40 8 0 4 8 1 5 pin 1 0.65 bsc seating plane 0.38 0.22 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.08 3.20 3.00 2.80 5.15 4.90 4.65 0.15 0.00 0.95 0.85 0.75 figure 28. 5-lead small outline transistor package (sot-23) (rj-5) dimensions shown in millimeters figure 30. 8-lead mini small outline package (msop) (rm-8) dimensions shown in millimeters ordering guide model temperature range package desc ription package option branding adcmp600brjz-r2 1 ?40c to +125c 5-lead sot23 rj-5 g0c adcmp600brjz-rl 1 ?40c to +125c 5-lead sot23 rj-5 g0c adcmp600brjz-reel7 1 ?40c to +125c 5-lead sot23 rj-5 g0c ADCMP600BKSZ-R2 1 ?40c to +125c 5-lead sc70 ks-5 g0c adcmp600bksz-rl 1 ?40c to +125c 5-lead sc70 ks-6 g0c adcmp600bksz-reel7 1 ?40c to +125c 5-lead sc70 ks-6 g0c adcmp601bksz-r2 1 ?40c to +125c 6-lead sc70 ks-6 g0n adcmp601bksz-rl 1 ?40c to +125c 6-lead sc70 ks-6 g0n adcmp601bksz-reel7 1 ?40c to +125c 6-lead sc70 ks-6 g0n adcmp602brmz 1 ?40c to +125c 8-lead msop rm-8 gf adcmp602brmz-reel 1 ?40c to +125c 8-lead msop rm-8 gf adcmp602brmz-reel7 1 ?40c to +125c 8-lead msop rm-8 gf 1 z = pb-free part.
adcmp600/adcmp601/adcmp602 rev. 0 | page 15 of 16 notes
adcmp600/adcmp601/adcmp602 rev. 0 | page 16 of 16 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05914-0-10/06(0)

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